CODING INTERNATIONAL CO LTD

While punch throughs (PTs) are the preferred power device for a growing segment of industrial power conversion applications requiring operation from ac line voltages of 575Vac to 690Vac, historically, 1700V IGBTs based on a non punch through (NPT) structure were popular. For the NPT device to have stable leakage current at such high blocking voltages, a thick n- layer is necessary. However, the thick n- layer leads to high losses due to increased VCE(sat) and tail current.

An alternate approach is to use an epitaxial buffer layer chip (PT structure) that yields lower losses. However, the very thick epitaxy required for high blocking voltages substantially increases fabrication costs. To circumvent these problems, the development of a new 1700V IGBT chip is possible by adopting a single crystal (non-epitaxial) wafer with a diffused buffer layer (PT structure) and local lifetime control (Fig. 1a).

Chip Comparison

You can roughly categorize IGBTs according to their main voltage blocking structure. The punch through (PT) IGBT uses a lightly doped high resistivity n- layer along with a more heavily doped field stopping layer to block voltage. In the off state, the electric field reaches through the n- region until it touches the buffer layer (punch through). The non punch through (NPT) IGBT has a homogeneous n- layer in which the resistivity and thickness are optimized to support the desired blocking voltage. This eliminates the need for a buffer layer.

Recently, manufacturers successfully produced IGBTs based on both structures for power conversion applications. By taking advantage of the key technologies developed during the continuous evolution and optimization of these competing structures, manufacturers have produced a new 1700V device exhibiting the best characteristics of both structures. To understand this new device we must first review the conventional PT and NPT structures.

PT IGBT

The first commercial IGBTs used a punch through (PT) chip structure. This structure is still the most common today. Manufacturers normally produce the PT IGBT using a starting material of positively-doped silicon (collector layer), on which the other layers are grown epitaxially (Fig. 1b). The well-controlled resistivity and thickness of the epitaxial n- layer in this structure allows the device to be highly optimized to meet the requirements of a target application. Today, the PT structure fabricates everything from extremely low switching loss devices, suitable for replacement of power MOSFETs, in applications such as switch mode power supplies to rugged high voltage types for industrial motor drives and traction applications.

To achieve low switching losses in a PT IGBT, you must accelerate the rate of recombination of charge (carrier lifetime) in the buffer layer. Historically, electron irradiation served this purpose. Electron irradiation creates recombination sites in the buffer layer, which yields increased turnoff speed and lower tail current losses. However, this process introduces recombination sites in the n- layer, which increases VCE(sat). This gives rise to a fundamental trade-off between VCE(sat) and switching losses. Heavy doses yield low switching losses and an increase in VCE(sat). The recombination rate set by the electron irradiation is temperature dependent — increasing switching losses at elevated temperatures.

A new lifetime control technique using proton beam irradiation [2] has virtually eliminated these problems in the latest generation of epitaxial PT IGBTs. With proton beam irradiation, you can adjust the energy level to introduce recombination sites within the buffer layer without affecting the n- region. The result is low VCE(sat) and low switching loss at elevated temperature. Clever use of lifetime control processing helps with optimization of dynamic characteristics for reduced switching noise and transient voltages.

The cost of the epitaxial silicon is a drawback of this type of PT structure. This is a significant factor in the case of rugged high voltage (VCES>1200V) industrial devices that require thick n- layers to achieve desired blocking voltage and ruggedness.

NPT IGBT

Non punch through (NPT) IGBTs are developed using a homogeneous silicon starting material into which the collector and other layers are diffused (Fig. 1c, on page 28). In this structure, the thickness and resistivity of the n- layer adjusts to achieve the desired blocking voltage capability without relying on a field stopping buffer layer. Typically, the n- region in the NPT device is considerably thicker than PT devices. This gives rugged SOA characteristics that are desirable for many industrial applications. However, the thick n- layer also yields a higher VCE(sat). To reduce the VCE(sat) of the NPT IGBT, you must reduce the thickness of the n- layer by using thinner silicon wafers for starting material. The latest generations of NPT IGBTs use special thin wafer processing technologies to lower VCE(sat). A side effect of these processes is increased leakage currents, which in the end often necessitate the use of a thicker n- than PT devices of similar voltage ratings.

The lack of a buffer layer in the NPT IGBT makes lifetime control processing unnecessary. As a result, the temperature dependence of switching losses is less than PT IGBTs fabricated using conventional electron irradiation for lifetime control processing. The lack of lifetime control produces a long low-level tail current. Switching loss measurements truncated at 5% to 10% of rated current often ignore the switching losses associated with these tail currents.

The homogenous float zone silicon material used in the NPT IGBT is lower cost than the epitaxial silicon utilized in most PT devices. This becomes a significant factor in high voltage devices that require thick n- layers.

Another common side effect of the NPT chip design is a positive dependence of VCE(sat) on temperature over a wide range of current. This characteristic causes an undesirable increase conduction loss at elevated temperature, but facilitates current sharing in applications requiring parallel operation of IGBT modules.

1700V IGBT

An analysis of the characteristics and performance of PT and NPT IGBT processes and structures have lead to the following design targets for the new 1700V IGBT chip.

        The n- drift region should be as thin as possible to give a low VCE(sat). However, you should do this without compromising short circuit robustness or switching SOA.
       An n- buffer layer is necessary to secure a sufficiently high breakdown voltage and low leakage current in the presence of an optimally thin n- drift region.
       You should optimize lifetime control and buffer layer doping to produce a lower cross-point of the VCE(sat) vs. current characteristic, thereby achieving a positive temperature coefficient of VCE(sat).
       Base silicon material should be low cost single crystal (non-epitaxial) material.
Fig. 1a, on page 28, shows the structure of the new IGBT compared with the conventional PT (Fig. 1b) and NPT (Fig. 1c) structures. Manufacturers produce the new 1700V IGBT chip, designated “K-Series,” from an n- type single crystal wafer, in which a thin boron diffused layer forms the collector. Selecting the thickness of the n- drift layer so the depletion region extends to the collector when you apply rated voltage in the off-state leads to a thicker drift region than in the conventional PT structure. Proton irradiation at the border of the drift and collector layers, followed by annealing forms the n- buffer. Adjusting the anneal time controls the on-state voltage of the IGBT.

K-Series IGBT Characteristics

You can see the saturation voltage characteristic of a 150A, 1700V IGBT module in Fig. 2. This plot shows the new IGBT has a positive temperature coefficient of VCE(sat) over the normal operating current range. Compared with a conventional NPT device, this new device has the positive temperature dependence of VCE(sat) desirable for parallel operation. The new device is weaker, so the loss penalty at elevated operating temperatures is less severe. Figs. 3 and 4 show the inductive load turn-on and turnoff characteristics of the new IGBT.

The turnoff waveform shows the short duration tail current typical of a PT IGBT with lifetime control processing. Optimization of the lifetime control also allowed the reduction of the turnoff di/dt to prevent the severe transient voltages typical of many NPT designs.

The turn-on waveform shows the recovery characteristic of the newly developed soft recovery free wheel diode utilized in the K-Series modules. The adoption of an optimized proton beam irradiation profile ensures soft recovery over a wide range of currents and temperatures. Compared with conventional fast recovery diodes, this provides a significant reduction in recovery oscillations and the resulting EMI noise.

The SOA test result in Fig. 5 demonstrates device robustness. This shows a 150A device switching at more than three times rated current, which is a sufficient margin for the normal guaranteed SOA rating of two times nominal current.

The 1700V IGBT was designed to survive a low impedance short circuit with an 1100Vdc bus. Fig. 6 shows the current and voltage waveforms for a low impedance short circuit test. This waveform shows you can safely turn it off after a 10 μsec short circuit.

Module Package

To obtain maximum performance from the 1700V IGBT chips, an optimized module package and a free wheel diode with improved fast, but soft recovery characteristics were developed. The “U-Package” technology, developed by Mitsubishi in 1996 [9], is the basis for this IGBT module package.

Fig. 7 shows a cross section drawing of the new package. The key innovation is the insert-molded case in which the power electrodes are molded into the sides as opposed to inserted after the case is molded. The main electrodes then connect directly to the power chips using large diameter aluminum bonding wires rather than solder.

One of the main objectives in the design of the new package was a reduction in internal inductance. The most significant improvement was possible by molding wide electrodes into the sides of the case to form parallel plate structures having considerably less inductance than conventional electrodes. In addition, the strain relieving “S” bends that were needed in the electrodes of conventional modules are not needed in the U-Package because the aluminum bond wires perform the strain relieving function. Elimination of these “S” bends helped to further reduce the electrode inductance.

As an overall result of these inductance-reducing features, the new package has about one-third the inductance of conventional modules. The resistance of the electrodes has a more significant reduction compared with conventional modules, which reduces self-heating and improves reliability in high current applications.

Reducing the required number of soldering steps in the new module package (from two to one) allows for high speed automated assembly and testing. With the conventional module, you made the chip to substrate and substrate to baseplate soldering first with high temperature solder. Then, you attach the case to the baseplate and you use a second low temperature-soldering step to connect the power electrodes. In the new module, you can eliminate the second step because aluminum bond wires create the connections to the power electrodes.

The soldering process for chip and substrate attachment minimizes the effects of mismatched coefficients of expansion between the baseplate and the AlN (aluminum nitride) DBC (direct bond copper) substrate. The results are a reduction in stress during manufacturing, improved baseplate flatness, and increased reliability. Fig. 8, on page 38, illustrates the improvement in power cycling capability.

Another advantage of the new package is the substantially smaller ceramic substrate. The ceramic area needed for soldering the power electrodes in the conventional module is not a requirement. As a result, you can use higher performance AlN ceramic in a cost effective manner, to minimize the thermal impedance of the new package. The smaller ceramic geometries also reduce leakage capacitance to the baseplate, which is a major source of conducted EMI. The typical leakage capacitance of the U-Package is about one-third that of modules utilizing thin Al203 ceramics.